The present invention relates to the field of semiconductor memory devices; more specifically, it relates to a static random access memory (SRAM) formed on a silicon-on-insulator (SOI) substrate and the method of fabricating the SRAM.
NFET and PFET devices fabricated in SOI technology offer advantages over bulk devices. The advantages include reduced junction capacitance, reduced junction leakage current, and for fully depleted devices, reduced short channel effect, increased transconductance and reduced threshold voltage (VT) sensitivity. However, SOI FETs have a xe2x80x9cfloating body.xe2x80x9d The body or channel region of the FET is formed in an insulated pocket of silicon and is therefore not electrically connected to a fixed potential. One effect of the xe2x80x9cfloating bodyxe2x80x9d is to lower the VT of the device when the body xe2x80x9cfloats upxe2x80x9d. This is a particular problem in a SRAM cell as lowering the VT of the devices can cause the relative strengths of devices to change such that the cell flips when the state of the latch is read.
FIG. 1 is a schematic circuit diagram of a CMOS SOI SRAM cell. In FIG. 1, an SRAM cell 100 comprises a first input/output (I/O) NFET 105 and a second I/O NFET 110. SRAM cell 100 further comprises a first latch NFET 115, a second latch NFET 120, a first latch PFET 125 and a second latch PFET 130. The gate of first I/O NFET 105 is coupled to a wordline 135, the source of the first I/O NFET to a bitline 140 and the drain of the first I/O NFET to a first common node 145. The gate of second I/O NFET 110 is coupled to a wordline 135, the source of the second I/O NFET to a bitline-not 155 and the drain of the second I/O NFET to a second common node 160. The gates of first latch NFET 115 and first latch PFET 125 are coupled to second node 160. The gates of second latch NFET 120 and second latch PFET 130 are coupled to first node 145. The source of first latch NFET 115 is coupled to ground (GND) and the drain of the first latch NFET is coupled to first node 145. The source of second latch NFET 120 is coupled to GND and the drain of the first latch NFET is coupled to second node 160. Similarly, the source of first latch PFET 125 is coupled to VDD and the drain of the first latch PFET is coupled to first node 145. The source of second latch PFET 130 is coupled to VDD and the drain of the first latch PFET is coupled to second node 160. The bodies of all four NFETs 105, 110, 115, and 120 and both PFETs 125 and 130 are floating.
SRAM cell 100 is written to by writing bitline 140 high and bitline-not 155 low (or vice versa). SRAM cell 100 is read by activating either first I/O NFET 105 (or second I/O NFET 110) and sensing the current flow from bitline 140 (or bitline-not 155) to GND. If first I/O NFET 105 xe2x80x9cfloats upxe2x80x9d such that the VT of the first I/O NFET becomes lower than the VT of first latch NFET 115 (or second I/O NFET 110 xe2x80x9cfloats upxe2x80x9d such that the VT Of the second I/O NFET becomes lower than the VT of second latch NFET 120) SRAM cell 100 will become unstable and liable to flip states when read. A device with a low VT is a strong device.
In FIG. 1, first NFET 105 is designated as T1, second I/O NFET 110 as T2, first latch NFET 115 as T3, second latch NFET 120 as T4, first latch PFET 125 as T5 and second latch PFET 130 as T6. This convention is used in all subsequent figures as an aid to reading and comparing the drawings.
FIG. 2 is a partial cross sectional view of a portion of the SRAM cell of FIG. 1. FIG. 2 specifically shows the structure and wiring of second I/O NFET 110 and second latch NFET 120. Formed in a substrate 165 is a buried oxide layer 170 Formed on top of buried oxide layer 170 is a thin silicon layer 175. Formed in thin silicon layer 175 is an STI 180. STI 180 extends from a top surface 185 of thin silicon layer 175, through the thin silicon layer, to buried oxide layer 170. Formed in thin silicon layer is a source 190 of second latch NFET 120, a source 195 of second I/O NFET 110 and a common drain 200. Both second latch NFET 120 and second I/O NFET 110 share common drain 200. In silicon layer 175 and under a gate 205 of second latch NFET 120 is a second latch NFET body 210. In silicon layer 175 and under a gate 215 of second I/O NFET 110 is a second I/O NFET body 220. Source 190 of second latch NFET 120 is coupled to GND and gate 205 is coupled to first node 145. Source 195 of second I/O NFET 110 is coupled to bitline-not 155 and gate 215 is coupled to wordline 135. Common drain 200 is coupled to second node 160.
In FIG. 2, second I/O NFET 110 and second latch NFET 120 are illustrated as fully depleted devices. Thus, second latch NFET body 210 and second I/O NFET body 220 are co-extensive with what might otherwise be termed the channel regions of the respective devices. The actual channels themselves are formed in the respective bodies under their respective gates near top surface 185 of thin silicon layer 175.
FIG. 3 is a plan view of STI, gate, source/drain, contact and first wiring levels of a unit cell of the SRAM cell of FIG. 1. In FIG. 3, the shallow trench isolation (STI) level of SRAM cell 100 is defined by a first thin silicon region 225A and a second thin silicon region 225B. The extents of the silicon portions and the STI portions of SRAM cell 100 are set by first and second silicon regions 225A and 225B. The gate level is defined by a first gate conductor 240A, a second gate conductor 240B, a third gate conductor 240C and a fourth gate conductor 240D. First silicon region 225A is doped N+ where overlapped by an N+ region 250 except where first, second, third and fourth gate conductors 240A, 240B, 240C and 240D also overlap the first silicon region. The overlap of first silicon region 225A by first, second, third and fourth gate conductors 240A, 240B, 240C and 240D defines a first body region 250A, a second body region 250B, a third body region 250C and a fourth body region 250D respectively. Body regions 250A, 250B, 250C and 250D are doped P. First body region 250A divides first silicon region 225A into a first source region 255A and a first drain region 255B. Second body region 250B divides first silicon region 225A into a second source region 255C and a second drain region 255D. Third and fourth body region 250C and 250D further divide first silicon region 225A into a third source region 255E.
Second silicon region 225B is doped P+ where overlapped by a P+ region 260 except where third and fourth gate conductors 240C and 240D overlap the second silicon region. The overlap of second silicon region 225B by third and fourth gate conductors 240C and 240D defines a fifth body region 250E and a sixth body region 250F respectively. Body regions 250E and 250F are doped N. Fifth body region 250E divides second silicon region 225B into a third drain region 255F and a fourth source region 255G. Sixth body region 250F further divides second silicon region 225B into an fourth drain region 255H.
With reference to FIG. 1, first I/O NFET 105 comprises first source region 255A, first body region 250A, and first drain region 255B. Second I/O NFET 110 comprises second source region 255C, second body region 250B, and second drain region 255D. First latch NFET 115 comprises second source region 255C, third body region 250C, and third source region 255E. Second latch NFET 120 comprises third source region 255E, fourth body region 250D, and second drain region 255D. First latch PFET 125 comprises third drain region 255F, fifth body region 250E, and fourth source region 255G. Second latch PFET 130 comprises fourth source region 255G, sixth body region 250F, and fourth drain region 255H.
Also illustrated in FIG. 3 are a bitline contact 265 contacting first source region 255A, a ground contact 270 contacting third source region 255E, a bitline-not contact 275 contacting second source region 255C, a VDD contact 280, a first wordline contact 285A and a second wordline contact 285B. Wordline contacts 285A and 285B connect first gate conductor 240A and second gate conductor 240B, respectively, to a wordline 290. VDD contact 280 connects fourth source region 255G to a VDD power rail 295. A first node contact 300A connects first drain region 255B to first node conductor 305A. A second node contact 300B connects third drain region 255F to first node conductor 305A. A third node contact 300C connects gate conductor 240C to first node conductor 305A. A fourth node contact 300D connects second drain region 255D to second node conductor 305B. A fifth node contact 300E connects fourth drain region 255H to second node conductor 305B. A sixth node contact 300F connects gate conductor 240D to second node conductor 305B.
Because first body region 250A, second body region 250B, third body region 250C and fourth body region 250D, fifth body region 250E and sixth body region 250F are floating in FIG. 3, SRAM cell 100 is subject to random flips of state. Therefore, a technique of electrically connecting the bodies of SRAM FETs to a fixed potential, especially connecting all the NFETs to one fixed potential and all the PFETs to another, different potential, is needed to retain the advantages of SRAMs fabricated in SOI technology.
A first aspect of the present invention is a semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground.
A second aspect of the present invention is a semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in the thin silicon layer, each the I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region; and a first connecting region in the thin silicon layer abutting the body regions of the I/O NFETS, the first connecting region electrically connected to ground.
A third aspect of the present invention is a semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in the thin silicon layer, each the I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region; a first connecting region in the thin silicon layer, the first connecting region electrically connected to ground; and a pair of second connecting regions in the thin silicon layer, each second connecting region co-extensive with one of the body regions of the I/O NFETs and between the body regions and the first connecting region.
A fourth aspect of the present invention is a method of fabricating a semiconductor memory device comprising: providing an SOI substrate having a thin silicon layer on top of a buried insulator; forming an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs in the thin silicon layer, each the I/O NFET, latch NFET and latch PFET having a body region between source region and a drain region; forming a P+ doped first connecting region in the thin silicon layer abutting the body regions of the I/O NFETS; and forming a ground contact to the first connecting region.
A fifth aspect of the present invention is a method of fabricating a semiconductor memory device comprising: providing an SOI substrate having a thin silicon layer on top of a buried insulator; forming an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in the thin silicon layer, each the I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region; forming a P+ doped first connecting region in the thin silicon layer; forming a pair of second connecting regions in the thin silicon layer, each second connecting region co-extensive with one of the body regions of the I/O NFETs and between the body regions and the first connecting region; and forming a ground contact to the first connecting region.